Typically, and with reference to FIG. 1, one of the devices is designated as ‘master’ 10 and the other device or devices are designated as a ‘slave’ 20, which respond appropriately to all requests made to them from the master device. In conventional two-wire systems one of the wires 30 carries a clock signal and the other wire 40 carries data. The master device may carry out both read and write operations; in read operations a slave device will report data stored in a memory location within the slave device and in write operations the master device can update data stored within the slave device in order, for example, to alter the operation of the slave device.
In order to support compatibility and inter-operability between devices made by different manufacturers, industry standards have been developed and agreed. In the field of transceivers for datacommunications and telecommunications, agreed standards include SFF-8472 (Digital Diagnostic Monitoring Interface for Optical Transceivers, rev. 9.3, Aug. 1, 2002, published by the SFF Committee, http://www.sffcommittee.com/) which allows an extended feature set to be defined, SFF-8074i (also referred to as INF-8074I, Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA), rev. 1.0, Sep. 14, 2000, published by the SFF Committee) which defines a serial identification interface and SFF-8053 (GBIC (Gigabit Interface Converter), rev. 5.5, Sep. 27, 2000, published by the SFF Committee).
Typically in such schemes, the master device will initiate communication with a slave device by transmitting an 8-bit signal; the first seven bits of the signal correspond to the address of the slave device and the final bit indicates whether a read or a write operation is required of the device (conventionally, a read operation is denoted by a ‘1’ and a write operation is denoted by a ‘0’). Once the communication with the slave device has been established and a second 8 bit signal is sent to specify the memory location to which the read/write operation applies. If a read operation has been specified then the contents of the memory location are reported to the master device; if a write operation has been reported then a further 8 bit signal is sent to be slave device and written to the specified memory location. An inherent limitation of this method is that each slave device contains 256 bytes of information and with a 7-bit address space the maximum number of slave devices is 128. In practice, parts of the address space are reserved so that only 112 slave may be addressed. This limits the total addressable memory to 28,672 bytes.
The limits to the memory capacity of each slave device and the limit to the memory addressable by a master device pose significant issues. It may be possible to use a plurality of logical device addresses to refer to different memory areas of a single physical device but this can cause additional problems as many controllers can not address more than one logical device at the same time. Another known problem is that the implementation of the separation of read/write memory areas and read only memory areas within a single logical device can be difficult, as many devices only allow one type of memory area within a single logical device.
A number of solutions that address these problems have been proposed. In one, a specific request is sent to a reserved logical device address that causes the slave device to toggle between memory areas that are to be addressed (this is implemented within SFF-8472 as the Address Change function). This method is not generally supported and is error-prone and slower than conventional logic addressing. Another approach is to attach one or more memory devices (either physical memory or logical memory devices) to the serial interface bus. While it is not possible for the slave device to write directly to an individual memory device without preventing the master from reading data from that memory device (although this may be achieved by adding dedicated serial bus connections for each of the memory devices), it is possible for the master device to write data to all of the memory devices, with the slave device storing a master copy of the data so that any data that is incorrectly overwritten can be corrected before a subsequent read operation.
Another known technique (which is applicable in the case that the slave device is some form of micro-controller) is to not connect the serial interface of the micro-controller but to connect the clock and data lines to two general purpose digital input/output lines of the micro-controller. The inputs of the clock and data lines can be interpreted by the software and/or firmware of the micro-controller, which enables multiple logical devices to be addressed, and to a greater extent than is possible with the Address Call function, or other similar functions. The main disadvantage of such an approach is that a significant amount of processor time is used in the implementation of the method.